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Digital Lock Detector for Phase-Locked Loop Circuit

IP.com Disclosure Number: IPCOM000047745D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Keller, H Muller, HR [+details]

Abstract

A phase-locked loop (PLL) circuit for a communication system is provided with a digital lock detector. Details of such a lock detector are described in the following. One main application is in ring transmission systems operating with signals which are a Manchester code representation of the transmitted data. A block diagram of the digital lock detector is shown in Fig. 1, and respective waveforms are shown in Fig. 2. An associated phase diagram is depicted in Fig. 3. In the Manchester code, each data bit is represented by a pair of halfbits, e.g., a plus-minus pulse pair for a "1", and a minus-plus pulse pair for a "0".