Browse Prior Art Database

Multiprocessor Control of Cached Peripheral Systems

IP.com Disclosure Number: IPCOM000047749D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Hoskinson, WC Reed, DG [+details]

Abstract

A cached peripheral system, such as a tape or disk file peripheral storage system, has data transfers between an attached host processor and the cache simultaneous with the data transfers between the cache and peripheral data storage devices. Because of the rate of data transfers to and from the peripheral data storage devices, a single controlling processor is unable to appropriately supervise all the asynchronous data transfers. Accordingly, a secondary or slave "gap" processor closely supervises and controls the data transfers between the cache and the devices for relieving the other or main processor for operating the storage subsystem and performing other supervisory functions.