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Interstitial Vias for Improved Wirability

IP.com Disclosure Number: IPCOM000047773D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Girvan, EJ Overfield, RB Roberts, GC Teepan, TG [+details]

Abstract

The article describes an improved wiring scheme for printed circuit cards and boards which provide mid-channel escape. For 3 lines per channel printed circuit wiring random interstitial vias are used to enhance the escape of the center line. This maximizes the wiring capability of 3-line-per-channel printed circuits. It also provides a further increase in wiring density to 4 lines per channel. Access to the mid-channel lines is key to this extension. This improvement allows the use of 2-wiring-plane printed circuit boards in lieu of 3 and 4 wiring planes, the net result being increased productivity through design. This wiring scheme utilizes an interstitial via which is placed at random that is, where required, in the center of the standard grid matrix. Clearances between holes are thus maximized.