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In-Stream Logic Simulation Non-Orthogonality Verification for Current-Mode Logic Technology Collector Dotting

IP.com Disclosure Number: IPCOM000047792D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Davis, JW Jones, FD [+details]

Abstract

Non-orthogonality between collector dots of current-mode logic technology is checked and verified by means of conventional logic and error induction. The method involves checking and verifying the non-orthogonality of inputs to a current-mode logic technology output collector dot. Fig. 1 represents a version of current-mode logic gates configured with a collector ("C") dot. It shows two current-mode gates in output collector dot configuration. Arrows indicate possible current flow paths of each gate if non-orthogonality were not observed. The problem arises in that both gates are sourced by independent current elements with a common point of influence ("C" dot). If the dot terms from each gate were also allowed to be independent, a third logic state would be encountered.