Dynamic Testing of Multiple Embedded Arrays on the Same Chip by an Array Tester With Limited I/O Capability
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
The disclosed dynamic testing technique of multiple embedded arrays on the same chip by a limited I/O array tester can be illustrated with the following example: 1) Limitation of array tester: Total I/O's(signal) = 96 Maximum Data In(DI) or Data Out(DO) = 36 2) Embedded arrays: 16 X 45 with byte control of 18, 18 and 9 bits, i.e., 16 X 18, 16 X 18, 16 X 9. Signal I/O's for these arrays: 4 address lines 3 R/W lines 45 DI's 45 DO's Total Signal I/O's = 97 This violates the limitations set forth in (1).