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Driver-Sequencing Circuit Disclosure Number: IPCOM000047842D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue


Related People

Banker, DC Montegari, FA Norsworthy, JP [+details]


The driver-sequencing circuit (DSC) depicted in the drawing is designed to produce N100 ns delay from the time the input rises until the output rises. The delay is needed to sequence the off-chip driver circuits during testing. The sequencing avoids delta I problems that would otherwise occur as a result of many drivers switching simultaneously. The in-phase design of the DSC circuit allows the output of one circuit to trigger another; thus, the DSC circuits can be cascaded to sequentially turn on individual groups of off-chip drivers. Transistor T1 is an inverter that can be replaced by a T2L circuit if required by the specific application. With T1 off, current flows from +V through R1, R6, VbeT2, VbcT5, VbeT6 and SBD1 into ground. This turns T2 and T6 on, resulting in T3 off and T4 on.