DTL Compare Circuit
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Substantial speed improvement in a compare circuit is achieved by elimination of the current switch typically employed in the two-transistor compare circuit arrangements of the prior art. In the present scheme, the compare logic circuit employs two transistors and four diodes. Present transistor compare logic circuits normally comprise a 1 ma cascoded current-switch emitter follower with a delay time of approximately 800 picoseconds. In typical system arrangements, one of the critical timing parameters is the sum of the array access time and the compare time through the directory chip. In the exclusive-OR compare logic gate shown in the figure, this sum is reduced by approximately 0.5 nanosecond.