Byte Select Circuit for Low-Power Random-Access Memory
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
The byte select circuit shown in the drawing allows the dissipated power in a memory to be reduced, by preventing the current from flowing in the bit line of non-selected byte cells. In a random-access memory (RAM), comprising a matrix of HARPNP cells or Harper cells, a current is permanently flowing in the right and left bit lines RBL and LBL which are connected to the cells of the matrix columns. The byte select circuit has for a function the switching off of the current in the right and left bit line transistors TBR and TBL of the bit lines which are not selected, when a row of cells is accessed. It comprises a byte decoder circuit including true/complement generators (TCGs), and a byte Schottky barrier diode (SBD) matrix decoder.