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Circuit Structure for Measuring Delays of Logic Gates on Vlsi Chips

IP.com Disclosure Number: IPCOM000047867D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Oehmigen, D Vogel, A Wagner, O [+details]

Abstract

For bipolar TTL (transistor/transistor logic) and NMOS (nitride metal oxide silicon) circuits, the load resistor and the load device, respectively, define the DC power dissipation and the slope of the Toff delay (input pulse dropping) versus the capacitive load. A higher load resistance reduces the power required but leads to a greater divergence of the turn-on (input pulse rising) and turn-off delays of the gate for high capacitive loads. For many applications of logic chips, a time analysis, based on the average delay (Ton/2 + Toff/2), is sufficient. However, for optimizing the clock cycle times and for determining pulse drops, separate delay equations are used for Ton and Toff, taking into account that these delays depend on capacitive loads, fan-outs, dots, and additional pull-up devices.