Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08
The bus system shown in Fig. 1 consists of the bus units I to III with independent internal clock generators (not shown). In addition, the three bus units, which are interconnected by an address/data bus, may have a common clock system which emits time-skewed clocks, so that the three units have to work asynchronously. According to bus busy conditions, one of the bus units is granted access to the address/data bus by a bus arbitration unit. A line 11 for serial arbitration is arranged between bus units I, II and III. The lower part of the circuit diagram shows two clock lines 4 and 5 which control the information exchange between bus units I, II and III through the address/data bus. In contrast to previous bus systems, the present system is controlled in response to pulses 1 and 2 on lines 4 and 5 (Fig. 2).