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Single Mask Process for Polysilicon Gate Device Fabrication

IP.com Disclosure Number: IPCOM000047873D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Aboelfotoh, MO Polcari, MR Tsang, YL [+details]

Abstract

In a process for making FET devices having two polysilicon gates, contact windows or openings for providing interconnecting metal layers to be electrically connected to the source and drain diffused regions 12, the first polysilicon layer 14 and the second polysilicon layer 16 are formed in the silicon dioxide layer 18 using one masking step, and contact windows or openings to the silicon substrate 10 are formed in the silicon dioxide layer 20, as shown in Fig. 1, using a second masking step. The need for two masking steps is primarily due to the fact that the silicon dioxide layers 18 and 20 have different thicknesses.