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Mp/Dynamic Memory Synchronizer

IP.com Disclosure Number: IPCOM000047874D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Babcock, AS Braidt, JW [+details]

Abstract

This article describes a sequential logic arrangement for providing synchronization between a microprocessor and a dynamic memory which requires refresh. The synchronizer is shown in Fig. 1, and the timing diagram, shown in Fig. 2, illustrates its operation, for example, when a request for a refresh cycle occurs between the rise and fall of an oscillator pulse. Initially, let it be assumed that all of the flip-flops 2, 4, 10, 12 and 30 and the latch 26 are held in their OFF state due to negative signals maintained at their reset inputs. The fact that the sequential flip-flops 2, 4, 10 and 12 are in their OFF state is detected by the AND invert circuit 24 to maintain a negative signal, via the ALL FF OFF line and NOR invert circuit 34 on the first leg of the NAND circuit 38.