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Buffered and Gate

IP.com Disclosure Number: IPCOM000047885D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Boyle, DH Kouba, DJ [+details]

Abstract

An AND gate circuit is shown in the figure. The circuit is organized into three stages: the first stage being a serially connected arrangement of three FET devices 1, 2 and 3, the second stage being a serially connected arrangement of three FET devices 4, 5 and 6, and the third stage being a serially connected arrangement of two FET devices 7 and 8. Of particular interest is the use of "natural threshold" FET devices 1 and 2 in the first stage and 7 in the third stage, along with the use of a depletion-mode FET device 3, connected between the output node of the first stage and ground potential. In operation, the circuit carries out the AND logical function. There is a bootstrapping effect for the natural FET device 2 when the node between devices 2 and 3 is rising.