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Dynamic L1/Static L2 Merged CMOS Register Circuits

IP.com Disclosure Number: IPCOM000047998D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Thoma, NG [+details]

Abstract

Circuits are described that provide the capability to include fairly dense Shift Register Latch (SRL) circuits on a cascode voltage switch masterslice. The circuits include a dynamic L1 - static L2 register latch that is well adapted as a macro element in a cascode logic system. A circuit masterslice customarily includes a brickwalled set of circuits. For example, these may be differential NMOS transistor pairs with a shared source diffusion. Any circuit implemented has to have a circuit topology that uses the available transistors in pairs; otherwise, there will be a layout inefficiency. Also, the limited number of P-load devices forces the best designs to fit the input multiplexing or logic functions into a "tree" format, which may be the intent in the use of the masterslice.