Browse Prior Art Database

Installing an Instruction-Buffer on a Processor Memory Interface

IP.com Disclosure Number: IPCOM000048000D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Herrman, BD Jones, JF Maule, WE Thatcher, LE Villante, AE Wyatt, VD [+details]

Abstract

A Processor Memory Interface, such as in an IBM Series/1 processor memory interface,has increased performance for instruction fetches by prefetching instructions and storing them in a high speed instruction-buffer. Prefetching of instructions for storage in an Instruction-Buffer (I-Buffer) can be easily accomplished using the fact that instructions are stored sequentially in memory. The first step is to divide the memory into even and odd word banks so two words can be accessed at one time. When the CPU first requests an instruction fetch, a restart occurs.