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Three Input Exclusive OR

IP.com Disclosure Number: IPCOM000048031D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Puri, YK Widiger, DJ [+details]

Abstract

A three input exclusive OR circuit is disclosed in the figure. The circuit consists of a first cross-coupled pair of FET devices Q1 and Q2 which are cascaded with a second cross-coupled pair of FET devices Q3 and Q4, to perform a three input exclusive OR function. The truth table for the circuit shown in the figure is illustrated below, with input A0, A1 and A2 and output 40.