Soft Error Rate Reduction in Circuits by Selective Application of Protective Barriers
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
Patterned buried regions are incorporated near the most critical circuit areas on a VLSI (very large scale integration) chip. The resulting potential barrier near such critical circuit areas "steers" alpha particle generated charge carriers away from those critical circuit areas, whereby the "soft error" rate of the VLSI chip is substantially reduced.