Ground Buffer Circuit for Read-Only Memory Array
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08
This circuit enables decreased access times and reduced power consumption in MOSFET (metal oxide silicon field-effect transistor) source follower read-only memory arrays by providing a buffered ground circuit for the bit lines which biases the bit lines at a voltage above ground and below the threshold voltage of the data sensing circuits. Power dissipation is reduced because the bit line voltage swing is reduced to less than that of full FET logic levels.