Browse Prior Art Database

Controlled Gate 1 Dip Etch for Improved Poly 1 to Poly 2 Yields

IP.com Disclosure Number: IPCOM000048149D
Original Publication Date: 1981-Dec-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Barile, CA Brown, DK Seeley, G [+details]

Abstract

In the double polysilicon process, an inherent yield exposure on first polysilicon layer (poly 1) to second polysilicon layer (poly 2) shorts exists with the current technology. After the poly 1 electrode is delineated by CF(4)/0(2) reactive ion etching and prior to gate 2 oxidation, a wet dip etch of the remaining exposed gate 1 silicon dioxide is made. It has been found that control of this gate 1 dip etch is a critical step in creating good quality poly 1 to poly 2 structures.