Browse Prior Art Database

ECL to TTL Translate Circuit for Laserable PLA

IP.com Disclosure Number: IPCOM000048329D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Flaker, RC [+details]

Abstract

This article discloses a programmable ECL (emitter coupled logic) to TTL (transistor transistor logic) translation circuit which can be pretested before programming. Shown is an ECL circuit comprising transistors 1 through 11 and diodes D1 through D6. Latch offset signals M and M/-/ are received from a latch circuit (not shown) and translated through buffer transistors 2 and 3 and diodes D1 and D2 to the bases of transistors 5 and 6. A single composite transistor could be substituted for transistors 5 and 7 and the diode D4. Similarly, a simple composite transistor could be substituted for transistors 6 and 8 and the diode D3. In any event, these devices together with the resistors R1 and R2 form a current switch that drives the current mirror comprised of transistor 11 and diode D5.