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D-Type Latch Disclosure Number: IPCOM000048410D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2005-Feb-08

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Puri, YK Widiger, DJ [+details]


An FET latching circuit is disclosed which provides a self-generated dual-clocking operation. Data input A is applied to the source of transistor T1, and the clock input C is applied to the gates of the transfer device T1 and the active device T2. When the clock pulse C makes a transition upwardly, both T1 and T2 are turned on. T1 transfers the logic state of A to the gate of transistor T3, and when C makes a transition downwardly, the charge transferred through transistor T1 is stored in the node 1 of the gate of transistor T3. Transistor T2, in its momentary on state, transfers the gating pulse to the gate of transistor T4 which serves to transfer any signal stored at the node 2, which is the drain of the device T3, to the gate of the transistor T5, which is the node 3, at which an information state will be stored.