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MTL Array Restore Technique Disclosure Number: IPCOM000048553D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08

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Hargrove, M Masenas, C Williams, T Zerr, P [+details]


This technique includes a circuit that is triggered to restore an array of merged transistor logic (MTL) cells to a reference that tracks with the cells and then resets itself automatically. By employing this technique, the need for generating a fixed restore time is eliminated, resulting in an improved array cycle time. An MTL memory cell is described in some detail in U.S. Patent 4,158,237.