On-Chip Refresh Address Counter Circuit
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08
This article discloses a new refresh address counter imbedded in an address true/complement circuit which utilizes a significantly reduced number of devices while maintaining well-controlled read and write signals to the counter memory cell 10. Shown in the drawing is a true/complement latch 11 comprising a pair of cross-coupled FET devices which is coupled at one end to a first output driver 12. The other end is coupled to a second output driver 14. The input side of the latch on refresh cycles is coupled to ground through devices 15 and 16 and on read/write cycles to ground through devices 17 and 18. The refresh address counter circuit comprises devices 16, 19, and 20.