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Double Polysilicon FET Gate II Oxidation Anneal

IP.com Disclosure Number: IPCOM000048579D
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-08

Publishing Venue

IBM

Related People

Authors:
Barile, CA Brown, DK Hu, SM Martin, LK [+details]

Abstract

The double polysilicon FET gate process, which incorporates a heavily doped first polysilicon layer with a 800 degrees C steam/HCl second gate oxidation, can produce a structural defect in the resulting sidewall silicon dioxide. This flaw is a crack in the sidewall silicon dioxide which later fills in with the second polysilicon layer, which thus creates an electrically weak region. The cracking of tensile stressed regions occurs after the second gate oxidation terminates, and is most probably induced by exposure to chemicals. The prevention of sidewall silicon dioxide cracking can be accomplished by annealing the post gate II structure for 15 minutes at 1000 degrees C in N(2). The anneal, for which allows stress relief via viscous flow, must be applied prior to the second polysilicon layer deposition.