Programmable Accurate On-Chip Delay
Original Publication Date: 1982-Feb-01
Included in the Prior Art Database: 2005-Feb-09
For generating propagation delays on logic chips which generally consist of logic elementary blocks, such as NAND, NOR, AND, etc., the block delay of one logic elementary block is used. Depending upon the delay required, several such blocks are connected to form a block delay chain.