Browse Prior Art Database

Delay Line Controlled Channel To Channel Data Transfer Mechanism

IP.com Disclosure Number: IPCOM000048757D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Firth, SR Mitchell, MJ [+details]

Abstract

I/O device or channel design for certain data processing systems must contend with the problem of synchronizing data tags with their internal clocking mechanism. In the case of a channel, the data tags must eventually be synchronized with storage clocking. In the case of I/O devices, the data tags must be synchronized with the clocking of the storage media (tape, disks, etc.). This is particularly troublesome because metastability must be taken into account anytime that an asynchronous tag has to be synchronized with a clock timing pulse during the possible period of instability following the sampling. The usual solution is to wait over this metastable duration before actually using the asynchronous data.