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Bipolar Transistor Structure

IP.com Disclosure Number: IPCOM000048778D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

A method is disclosed to fabricate very compact transistors wherein both base and collector metal contacts are merely a submicron distance away from the emitter. The process sequence is preferably as follows: 1. Obtain the structure of Fig. 1 following a conventional basic process sequency up to the Si(3)N(4) deposition. 2. Form patterns in Si(3)N(4) layer 16 using a photoresist mask and RIE (reactive ion etch). Retaining the resist mask, ion implant a thin layer 18 of N+ impurity. 3. Through CVD (chemical vapor deposition), deposit approximately 8000 angstroms polysilicon 20 and approximately 800 A A Si(3)N(4) 22, this latter thickness being designed much much thinner than Si(3)N(4) layer 16 (Fig. 2). 4. Through photoresist masking and RIE, form patterns in Si(3)N(4) 22 and polysilicon 16 (Fig.