Dielectric Breakdown Identification For Very Large Scale Integration
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
In order to do failure analysis of a shorted array or circuit in a silicon chip, first it is required to define the exact location of the defective cell or gate. Present techniques use liquid crystal solutions, which involve long and complicated sample preparation, to identify tify general areas, within 20 to 40 Mum in diameter, where the defect is located. The improved technique allows the user to identify the exact location within 1 Mum radial area so an exact cross-sectional analysis can be done for the defect characterization. This technique is important for interlevel shorts In double polysilicon structures or to highlight the weak design areas on newly released designs.