Browse Prior Art Database

Creation of Super Instructions In Hardware

IP.com Disclosure Number: IPCOM000048893D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Agerwala, TK Rao, GS Sachar, HE Weiss, JA Yamour, J [+details]

Abstract

High performance processors like the IBM System/370 Model 3033 use a hardwired instruction preprocessing function unit (IPPE) and microcoded execution (E) unit. An ideal instruction goes through the pipelined lined machine in four cycles as follows: In the first cycle (D/A), the instruction is decoded to determine the needs in terms of general purpose registers (GPRs) and operands from cache, and information relevant to its execution activity is placed in a four-position queue between the IPPF and the E unit. In the next cycle (C1), the operand access for the instruction if any is begun.