Borderless N+ Contact in Fet Device
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
A field-effect transistor device has been formed which includes a P-substrate 10, recessed dielectric isolation 12, N+ source/drain region 14 and silicon dioxide layer 16 on the surface of region 14. The figure shows this structure after the contact opening has been formed through the silicon dioxide layer 14 using conventional lithography and etching processes.