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High Density, High Performance Fet Process and Structure

IP.com Disclosure Number: IPCOM000048976D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Malaviya, SD [+details]

Abstract

The present process produces self-aligned gate, self-aligned field oxide, reduces source and drain capacitances drastically, and reduces gate delay. The process outline is as follows: 1. Provide P-substrate 10, form screen silicon dioxide, deep boron implant for threshold adjustment (optional), and anneal. 2. Strip screen silicon dioxide, regrow gate silicon dioxide 12 for better gate integrity. Grow thin silicon nitride 14, if a composite oxide/nitride gate is desired. 3. Deposit about 3000 angstroms or more of polysilicon 15, then another thin layer, 500 angstroms of silicon nitride 16. 4. Chemical vapor deposit (CVD) polysilicon, about 1 micron thick.