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Described herein is a fabrication technique to realize polysilicon resistors of both low and high sheet resistivity. The resultant planar planes.
English (United States)
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Polysilicon Resistor Integrated Planar Design
Described herein is a fabrication technique to realize polysilicon resistors of
both low and high sheet resistivity. The resultant planar planes.
Fig. 1 illustrates the basic semiconductor structure required to fabricate the
polysilicon resistor. A double application of polysilicon is done as depicted in Fig. 1. A blanket ion implant of boron is done to convert the polysilicon II into
approximately 1K ohm per square. Subsequently, a planarizing photoresist is
spun on the semiconductor structure depicted in Fig. 1. Masking protection of
the photoresist for formation of the polysilicon II is depicted in Fig. 2.
RIE (reactive ion etching) of the polysilicon II will provide polysilicon II for
resistor definition and sidewall for stud separation of metal lands. Oxidation of
the remaining polysilicon II will form the stud. Deposition of nitride and the
subsequent implanted emitter masking step will open all N+ contacts. However,
the polysilicon II used for defining the resistor will remain protected and is shown
in Fig. 3.
The remaining nitride, used to protect the polysilicon I, is removed as well as
the nitride protection of the polysilicon II high spots over polysilicon I. Fig. 4
shows the cross section prior to polysilicon wet etch. This wet etch will remove
all of the polysilicon I and the high spots of polysilicon II. The nitride protection is
then removed from above the polysilicon II resistor to provide electrical c...