Browse Prior Art Database

Shift Register Latch Driver

IP.com Disclosure Number: IPCOM000049002D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Diepenbrock, JC Gaudenzi, GJ Reedy, DC [+details]

Abstract

A design structure called Level Sensitive Scan Design (LSSD) has been described in U.S. Patent 3,783,254. The purpose of LSSD is to enhance testability of complex logic networks. This is achieved by requiring all latches in a given sequential network to be part of shift register latches (SRLs). These SRLs are tied together to form one or more shift registers whose contents are controllable from scan-in primary inputs (PIs) and scan clocks, and observable at scan-out primary outputs (POs). The effect of these SRLs is to provide an equivalent to electrical test points at those locations in the network where the SRLs are placed.