Browse Prior Art Database

Modular Buffer Allocation Control Logic Disclosure Number: IPCOM000049057D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue


Related People

Haigh, DC [+details]


This article describes a way of controlling several data buffers which are being filled (written) and emptied (read) in sequence, when the writing and reading occur asynchronously and/or at different data rates. The logic to control the buffers must indicate which buffers should be written and read next, and must also indicate when no buffers are available for writing or reading. The data in each buffer is treated as a complete entity and no attempt is made to take advantage of known different data rates to allow writing and reading of the same buffer simultaneously. This will allow error recovery procedures to be implemented whereby a write or a read may be retried before declaring a buffer to be full or empty.