Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Reduction Of Punchthrough In Josephson Latching Circuits

IP.com Disclosure Number: IPCOM000049082D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Gheewala, TR [+details]

Abstract

In Josephson device circuitry, a condition known as punchthrough can occur. In this condition, a Josephson device may not reset when the gate current through it goes through zero. This article describes a technique for reducing the probability of punchthrough by using two or more Josephson devices having uncorrelated phases, the Josephson devices being interconnected by small resistors. This circuit effectively reduces the load impedance as seen by the Josephson devices and thereby reduces their punchthrough probabilities.