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2R 1W Static RAM Cell

IP.com Disclosure Number: IPCOM000049164D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Chin, WB Wong, RC [+details]

Abstract

Three port RAMs (random-access memories) with two read ports and one write port are needed for many processor designs. The conventional implementation of the two read port functions uses two sets of output devices in the RAM cell, and two sets of word lines, bit lines and the associated drivers and sensing circuits. It was proposed that one set be used to provide the two port functions. Extra voltage levels are introduced by the read word line to indicate whether it is selected by port 1 or port 2 or by both. Extra bit line output voltage levels are generated to carry two bits of information, for port 1 bit and port 2 bit. This article illustrates the ideas with a design of a three-port RAM with an organization of 64 x 18.