Browse Prior Art Database

High Speed Virtual FIFO Memory

IP.com Disclosure Number: IPCOM000049179D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Tast, HW [+details]

Abstract

A so-called FIFO (first-in, first-out) memory consists of a register chain. A data word is written into the first register of the chain, setting an associated note bit. If this note bit is not active for the second register of the chain, a data word is transferred from the first to the second register, erasing the note bit of the first register. In this manner, the data word moves down the register chain until it reaches an occupied register. The data word written in first moves straight to the output of the FIFO memory. The disadvantage of known FIFO memories is that their capacity is rather limited and that any capacity increase leads to excessive fall through times, making such memories unsuitable for practical use.