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Decoder Current Distribution System

IP.com Disclosure Number: IPCOM000049180D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09

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Related People

Klein, W Klink, E Najmann, K Wernicke, FC [+details]


For selecting an address in a storage array chip, a decoder matrix is used which is subdivided in the X- and Y- and the word and bit direction, respectively. If a plurality of data channels are implemented on a chip, each bit decoder must be capable of addressing one data channel. In an array with a word length of 10 bits, for example, each data channel has 10-bit line channels. Assuming that 16 data channels are arranged in bit line direction, then one out of 16-bit decoders must simultaneously select 10-bit line channels. This leads to relatively high currents.