High Speed Clock Generation
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Generating clock signals with periods approaching 20 ns requires device with minimal propagation delay. Schottky TTL (transistor-transistor logic) LSI (large-scale integration) parts, such as counters and dividers, have delays which prevent use at this high speed. Clock skew becomes a problem when multiple signals are decoded from the same signal source since delays vary through different signal paths.