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Integrated Circuit Chip Passivation Etching Technique

IP.com Disclosure Number: IPCOM000049285D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09

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Betz, PW Motsiff, WT [+details]


This technique reduces fracturing and chipping of integrated circuit passivation layers during chip dicing by removing a narrow strip of the passivating layer around the perimeter of individual chips at the time via holes are etched through the passivation layer.