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ESD Protection Without Parasitic NPN

IP.com Disclosure Number: IPCOM000049347D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Knepper, LE [+details]

Abstract

An arrangement is described to provide electrostatic discharge (ESD) protection to chip I/O terminals without the parasitic NPN transistor action which accompanies conventional ESD protection schemes.