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The circuit described here is an implementation of a Shift Register Latch, used as described in U.S. Patent No. 3,783,254, in conjunction with a controlled switching transition rate off-chip driver circuit.
English (United States)
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Driver with Built-In Shift Latch
The circuit described here is an implementation of a Shift Register Latch,
used as described in U.S. Patent No. 3,783,254, in conjunction with a controlled
switching transition rate off-chip driver circuit.
A block diagram of the driver is shown in Fig. 1, which is a standard design in
logical function, while the schematic diagram (Fig. 2) shows the unique
implementation of the function within the driver circuit itself. The driver circuit
includes a polarity hold Ll latch comprising T2, T3, D3-9, R3 and R4, and the
feedback path from the collector of T4 to D7. This latch will propagate data
directly through to the driver output when the C clock is active (+C=logic 1, -
C=logic 0), and latch the data present at the input when C is inactive (+C=logic 0,
-C=logic 1). Data can also be latched through the scan data input using the A
clock in a similar manner. Operation may thus be as a latched driver for system
use, or for testing using the Level Sensitive Scan Design method as described in
U.S. Patent 3,783,254, or both.
In order to minimize the area consumed and extra delay introduced as a
result of implementing the latch, transistors T1-T3 are fabricated as a single
three-base, three-emitter transistor with a common collector. D3-D9 are Schottky
barrier diodes, and R3-R4 are standard resistors. The L2 latch shown is a
standard polarity hold design.
The primary advantages of this circuit over previous designs