Memory Driver with Split Damping Resistor
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
The driver circuit illustrated in Fig. 1 is implemented in bipolar logic technology to interface to FET memories which require positive logic levels in excess of +2.8 V at 220 microamps DC and limited down going output transitions such that negative overshoots do not exceed 1.0 V. This driver circuit meets these requirements as described below.