Browse Prior Art Database

Prefetching in a Multilevel Memory Hierarchy

IP.com Disclosure Number: IPCOM000049471D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Bennett, BT Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]

Abstract

The key aspect set forth in the three-level memory hierarchy, comprised of level 1 (L1), level 2 (L2), and level 3 (L3), is the incorporation of the prefetching mechanism within the directory of the second level cache. An example of the value of this idea is sequential line fetching on Instruction Misses from the first level cache. If the prior sequential aspect of the line referencing has been maintained by the directory of the L2, then it need not be maintained separately by a Cache Miss History Table, resulting in a clear saving in hardware.