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Browse Prior Art Database

Pageable Memory Element Design

IP.com Disclosure Number: IPCOM000049480D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Parks, LS Losq, JJ Miranker, GS Sachar, HE [+details]

Abstract

This article describes a design to improve the performance of a small processor (microprocessor) on a set of applications which are regular. By regular we mean those in which a large part of the processing required can be viewed as the manipulation of an array of data such that the result is an array, and the manipulation can be decomposed into transformations of rows of the data. For example: F(DA(1))=DA(2) F(D)=(f(i))(f(2))......(f(n))(D) where (f(i)) maps rows to rows.