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Browse Prior Art Database

Address Generate Interlock Memory Buffer

IP.com Disclosure Number: IPCOM000049481D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Losq, JJ [+details]

Abstract

In pipeline processors, quite often the formation of operand addresses must be delayed because the components of that address, the base and index registers, are not yet available. This is referred to as an Address Generate Interlock (AGI). Address Generate Interlocks are of two types: those caused because the index or base register has to be modified in the E-unit by some preceding instruction before it can be used in the address formation (referred to as AGIL for logical AGI) and those caused because the index or base register has been fetched by a preceding instruction, but because of the memory (cache) access time, is not yet available. This last type of AGI will be referred to as AGIM (M to denote Memory). The idea presented herein is a method to avoid these AGIMs.