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Eliminating the Overhead of Floating Point Load and Store Instructions by Decoding Two Instructions Per Cycle in the Floating Point Unit

IP.com Disclosure Number: IPCOM000049484D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Agerwala, TKM Tomasulo, RM [+details]

Abstract

A floating point arithmetic unit is described in which two instructions per cycle are decoded. The store and load operations are overlapped in floating point loops.