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Zero Condition Code Detection for Early Resolution of BCS and BCRS

IP.com Disclosure Number: IPCOM000049485D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue


Related People

Losq, JJ Rao, GS [+details]


The outcome of truly conditional BCs (Branch Condition) and BCRs (Branch on Condition Register) depends on the branch mask value and on the condition code (CC) setting. For many instructions, condition code setting involves a complex operation. For example, for arithmetic operations, the CC setting indicates if the result is greater than, less than, or equal to zero. For logical operations, it indicates whether the first operand is greater than, less than, or equal to the second operand. In general, the condition code is not available until the instruction has been through the E unit. Hence, the resolution of any branch that depends on the CC setting must wait until the CC setting instruction has been through the execution unit (E unit). In pipeline machines, this causes some delay, i.e.