Array Cell Stability Monitor
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Each wafer with integrated memory chips comprises, in addition to product chips, so called test sites and a plurality of test structures in the kerf. The test site is adapted to the respective product chip; i.e., it has test structures made up of the elements and circuits contained in the product chip. For deriving the chip parameters from the test structures of the test sites or the kerfs, very elaborate test systems and evaluator programs as well as experts for interpreting the test data are required.