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FIFO Buffer with Variable Number of Words

IP.com Disclosure Number: IPCOM000049592D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Mitchell, RC Williams, G [+details]

Abstract

A first in, first out (FIFO) buffer has a number of word locations arranged conceptually in rows. For addressing, each row is connected to a stage of a shift register. When a 1 bit appears in a register stage, the corresponding word location is enabled for a read or write operation. To load the buffer, a single 1 bit is entered into the register and, with each shift, a new word is loaded into the next location of the buffer. For a read operation, the register is cleared and a 1 single bit is again shifted through the register to read the words in the same order in which they were written.